Multi-level voltage adjustment

ABSTRACT

An adjustable voltage supply ( 310 ) may have a plurality of levels of adjustment, such as a coarse select circuit ( 471 ) and a fine select circuit ( 473 ), to generate an adjustable voltage (e.g. Vout  364  of FIGS.  3  and  4 ) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array ( 300 ). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply ( 310 ) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply ( 310 ) may be used in any desired context, not just memories.

FIELD OF THE INVENTION

The present invention relates generally to voltage adjustment, and moreparticularly to multi-level voltage adjustment.

RELATED ART

Voltage adjustment circuits have a variety of uses. One possible use isto aid in the determination of threshold voltages. For example,nonvolatile memories may require that the distribution of bitcellthreshold voltages be determined in order to understand the marginalityof the bitcells with regard to a read voltage. Another possible use ofthe voltage adjustment circuits is to provide an adjustable electricalstress to the bitcells in a memory array in order to test the robustnessof the bitcells.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitedby the accompanying figures, in which like references indicate similarelements, and in which:

FIG. 1 illustrates, in block diagram form, an integrated circuit inaccordance with one embodiment of the present invention;

FIG. 2 illustrates, in graphical form, bitcell threshold voltagedistributions for erased bitcells and for programmed bitcells inaccordance with one embodiment of the present invention;

FIG. 3 illustrates, in block diagram form, a portion of flash memory 14of FIG. 1 in accordance with one embodiment of the present invention;

FIG. 4 illustrates, in block diagram form, a portion of an adjustablevoltage supply circuit of FIG. 3 in accordance with one embodiment ofthe present invention; and

FIG. 5 illustrates, in flow diagram form, a method in accordance withone embodiment of the present invention.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help improve theunderstanding of the embodiments of the present invention.

DETAILED DESCRIPTION

FIG. 1 illustrates, in block diagram form, an integrated circuit 10 inaccordance with one embodiment of the present invention. In theillustrated embodiment, integrated circuit (IC) 10 comprises one or moreprocessors 12, one or more flash memories 14, one or more other memories16, one or more other modules 18, and an external bus interface 20 whichmay be bi-directionally coupled by way of bus 22. Alternate embodimentsmay not have a processor 12, may not have other memory 16, may not haveother modules 18, and/or may not have external bus interface 20. In theillustrated embodiment, external bus interface 20 is coupled to anexternal bus 24 which may be used to communicate information to and fromIC 10. Flash memory 14 is coupled to one or more integrated circuitterminals 26 which may be used to communicate information between flashmemory 16 and circuitry (not shown) that is external to IC 10. In oneembodiment, an integrated circuit terminal 26 may be used to provide afixed voltage (Vfixed 410) to flash memory 14. In alternate embodiments,this fixed voltage may be provided by way of external bus interface 20and buses 22 and 24. In yet other embodiments, this fixed voltage may beprovided by way of an input terminal 28 coupled to an input port inother modules 18. In alternate embodiments, one or more of modules 12,16, and 18 may have one or more integrated circuit terminals (not shown)which may be used to communicate information to and/or from circuitry(not shown) that is external to IC 10. Note that in some embodiments, IC10 may have only one or more flash memories 14.

FIG. 2 illustrates, in graphical form, bitcell threshold voltagedistributions for erased bitcells and for programmed bitcells inaccordance with one embodiment of the present invention. In theillustrated graph, curve 200 shows the number of bitscells (see verticalaxis) that have the specified threshold voltage (see horizontal axis)when the bitcells in array 300 (see FIG. 3) are erased. In theillustrated graph, curve 202 shows the number of bitscells (see verticalaxis) that have the specified threshold voltage (see horizontal axis)when the bitcells in array 300 (see FIG. 3) are programmed. Note thatthe vertical axis uses a logarithmic scale. The gap between curve 200and curve 202 indicates the marginality of the bitcells with regard tothe voltage which is required to read the bitcells. Using the curves200, 202, it is clear that the read voltage must be in the range of 3.5volts to 5.8 volts. For most real world applications, a margin is addedon both sides of this range to ensure that the bitcells are readaccurately over a long period of time. Thus, the read voltage may bekept within a narrower range than of 3.5 volts to 5.8 volts. Forexample, the read voltage may be kept within a range of 4.3 volts to 4.5volts.

FIG. 3 illustrates, in block diagram form, a portion of flash memory 14of FIG. 1 in accordance with one embodiment of the present invention. Inthe illustrated embodiment, adjustable voltage supply circuit 310 may beused to provide an adjustable voltage (Vout 364) to the wordlines inorder to facilitate the measurement of the threshold voltages (Vt) ofthe bitcells in array 300. In the illustrated embodiment, this isaccomplished in the following manner. An adjustable voltage supply 310applies a voltage Vout 364 to block switch 322. Block switch 322receives a control signal 354 from memory controller 306. Block switch322 uses control signal 354 to determine whether or not to provide Vout355 to row decoder 302. Signals 352 are provided to row decoder 302 toselect one row or wordline in bitcell array 300. Once a wordline isselected in this manner, memory controller 306 provides a plurality ofcolumn select signals 356 to column decode and sense amplifier circuit308 in order select the desired column(s). Once the desired row andcolumn is selected, current from the desired bitcells in array 300 isavailable at the inputs to sense amplifiers in circuit 308. These senseamplifiers in circuit 308 convert the received current to data values(data lines 378) that can be read as the values stored in the selectedbitcells. Note that signals 368-370 provide the current from thebitcells to the sense amplifiers in circuit 308. Source control circuit312 receives and uses a plurality of control signals 358 from the memorycontroller 306 to determine whether to float or ground the common source372 for all of the bitcells in array 300.

In the illustrated embodiment, adjustable voltage supply circuit 310 mayalso be used to provide an adjustable voltage (Vout 364) to the isolatedpwells (PWs) and nwells (NWs) in order to apply electrical stress to thebitcells in array 300. In the illustrated embodiment, this isaccomplished in the following manner. An adjustable voltage supply 310applies a voltage Vout 364 to block switch 320. Block switch 320receives a control signal 350 from memory controller 306. Block switch320 uses control signal 350 to determine whether or not to provide theadjustable voltage Vout 374, 376 to wells in array 300. Note thatadjustable voltage supply circuit 310 may also be used to provide anadjustable voltage to the selected wells in array 300 during erasurethrough the same path 374, 376 and using memory controller 306 toprovide the correct control signals.

In the illustrated embodiment, memory controller 306 provides both acoarse select signal 362 and a fine select signal 360 to adjustablevoltage supply circuit 310. The coarse select signal 362 selects acoarse voltage, which is used as the base of fine voltage, and then thefine select signal 360 selects a fine voltage as the output voltage Vout364. In the illustrated embodiment, the maximum coarse voltage and themaximum fine voltage is determined by Vfixed 410. Adjustable voltagesupply circuit 310 may internally generate the minimum coarse voltage,and the minimum fine voltage is determined by the selected coarsevoltage. Although the illustrated embodiment only uses two levels ofvoltage adjustment, alternate embodiments may use any number of levelsof voltage adjustment.

FIG. 4 illustrates, in block diagram form, a portion of an adjustablevoltage supply circuit 310 of FIG. 3 in accordance with one embodimentof the present invention. Circuit 310 comprises a coarse select portion471 and a fine select portion 473.

The coarse select portion 471 will be described first. Coarse selectcircuitry 471 comprises a plurality of resistors connected in series toform a resistor ladder 402. Multiplexer (MUX) 400 is coupled to eachrung on the resistor ladder 402. Coarse select signal 362 may be used toselect one of the rungs or voltages of resistor ladder 402 to beprovided as an output 428. Some embodiments may use a switch 411 toreduce power consumption when circuit 310 is not being used. Alternateembodiments may not use a switch 411 but may directly couple the top(first terminal) of the resistor ladder to Vfixed 410. Circuit 450comprises an operational amplifier (op amp) 404 and an n-channel fieldeffect transistor 406 to generate a minimum coarse voltage Vmin 363. Opamp 404 has an inverting input coupled to receive a voltage Vref 408. Opamp 404 has a non-inverting input which is coupled to the bottom (secondterminal) of resistor ladder 402. The top of resistor ladder 402 iscoupled to Vfixed 410 by way of a switch 411. The coarse voltage rangefor the illustrated embodiment ranges from Vmin 363 as the minimum toVfixed 410 as the maximum. A first current electrode of transistor 406is coupled to the bottom of resistor ladder 402, a control electrode oftransistor 406 is coupled to the output of op amp 404, and the secondcurrent electrode of transistor 406 is coupled to a first power supplyvoltage (e.g. ground). In one embodiment, resistor ladder 402 comprisesten resistors, each having a resistance value of five kilo-ohms.Alternate embodiments may use any number of resistors, each of which hasany appropriate value.

The fine select portion 473 will now be described. Fine select circuitry473 comprises a plurality of resistors connected in series to form aresistor ladder 422. Multiplexer (MUX) 420 is coupled to each rung onthe resistor ladder 422. Fine select signal 360 may be used to selectone of the rungs or voltages of resistor ladder 422 to be provided as anoutput Vout 364. Circuit 451 comprises an operational amplifier (op amp)424 and an n-channel field effect transistor 426 to generate a minimumfine voltage Vmin 365. Op amp 424 has an inverting input coupled toreceive a voltage 428 from coarse select circuit 471. Op amp 424 has anon-inverting input which is coupled to the bottom (second terminal) ofresistor ladder 422. The top of resistor ladder 422 is coupled to Vfixed410 by way of a switch 411. The fine voltage range for the illustratedembodiment ranges from Vmin 365 as the minimum to Vfixed 410 as themaximum. A first current electrode of transistor 426 is coupled to thebottom of resistor ladder 422, a control electrode of transistor 426 iscoupled to the output of op amp 424, and the second current electrode oftransistor 426 is coupled to the first power supply voltage (e.g.ground). Note that for some embodiment, a current source 452 may becoupled between the second current electrode of transistor 426 and thefirst power supply voltage. Alternate embodiments may not have currentsource 452. Current source 452 may be used to limit the current throughresistor ladder 422 in order to provide power savings and may be used toincrease the predictability of the amount of current that Vout 364 mayprovide to its load. In one embodiment, resistor ladder 422 comprisessixty-four resistors, each having a resistance value of one and one halfkilo-ohms. Alternate embodiments may use any number of resistors, eachof which has any appropriate value.

As an example, in the illustrated embodiment, if Vfixed 410 is set to 10volts and Vref 408 is grounded, and the coarse select signal 362 selectsa coarse voltage of 4 volts (with a resolution of 1 volt), the fineselect signal may select a fine voltage of 5.50 volts in the rangebetween 4 to 10 volts (with a resolution of approximately 0.1 volt), asthe output voltage Vout 364. Alternate embodiments may use any desiredvoltages and voltage ranges. Although the illustrated embodiment onlyuses two levels of voltage adjustment, alternate embodiments may use anynumber of levels of voltage adjustment.

Note that the resistive elements in resistor ladders 400 and 422 may becomprised of one or more resistors, transistors (e.g. field effect,bipolar), diodes, switched capacitors, or any other electrical elementthat can be used to provide a resistance. Note that this circuit 310 maybe used in any type of memory. However, circuit 310 may be especiallyuseful for non-volatile memory (e.g. flash memory) which has a chargestorage structure where the stored charge affects the voltage threshold.

FIG. 5 illustrates, in flow diagram form, a method in accordance withone embodiment of the present invention. The flow 499 starts at box 500where a test of flash memory 14 (see FIG. 1) begins. From box 500, theflow 499 proceeds to box 502 where array 300 (see FIG. 3) is erased.From box 502, the flow 499 proceeds to box 504 where specific bitcelllocations in array 300 are programmed. Any desired pattern (e.g. allones, all zeros, checkerboard, diagonal, etc.) may be used to programarray 300. Note that in an alternate embodiment, step 504 may not beused if the pattern does not require programming of array 300. From box504, flow 499 proceeds to box 506 where the maximum voltage for thecoarse voltage range and the maximum voltage for the fine voltage range(Vfixed 410) are set to a desired voltage level (see FIG. 4). Note thatin alternate embodiments, voltage for the top of resistor ladder 402 maycome from an alternate supply.

From box 506, flow 499 proceeds to box 508 where the value of Vmin 363(see FIG. 4) is selected by adjusting internally generated Vref 408.Vmin 363 and coarse select signal 362 are used to determine the voltageoutput 428 from the coarse select circuitry 471. From box 508, flow 499proceeds to box 510 where the value of Vmin 365 (see FIG. 4) isdetermined by the voltage output 428 from the coarse select circuitry471. Vmin 365 and fine select signal 360 are used to determine thevoltage output Vout 364 from the fine select circuitry 473. From box510, flow 499 proceeds to box 514 where the bitcells of array 300 areread to determine the conductivity of each bitcell. Note that thevoltage Vout 364 (see FIGS. 3 and 4) is used to read the bitcells. Frombox 514, flow 499 proceeds to box 518 where the number of bitcells thatare conductive at this particular Vout 364 is determined. Note that thenumber of conducting bitcells and the read voltage (Vout 364) may beused to form the erase curve 200. Note that to form the program curve202, step 518 may also include determining the number of non-conductivebitcells. The number of non-conductive bitcells may be determined bysubtracting the number of conductive bitcells from the total number ofbitcells in array 300.

From box 518, flow 499 proceeds to decision diamond 520 where thequestion is asked “are all bitcells conductive?” at this particular Vout364. If the answer is “yes”, then flow 499 proceeds to box 526 where thetest is finished. If the answer from decision diamond 520 is “no”, thenflow 499 proceeds to decision diamond 522 where the question is asked“have all fine voltage levels at this coarse voltage level (428, seeFIG. 4) been tested?”. If the answer is “no”, then flow 499 proceeds tobox 516. At box 516, the fine voltage level is adjusted (e.g. using fineselect 360, see FIG. 4). From box 516, flow 499 proceeds to box 514. Ifthe answer to decision diamond 522 is “yes”, then flow 499 proceeds tobox decision diamond 524 where the question is asked “have all coarsevoltage levels been tested?”. If the answer from decision diamond 524 is“no”, then flow 499 proceeds to box 512. At box 512, the coarse voltagelevel is adjusted (e.g. using coarse select 362, see FIG. 4). From box512, flow 499 proceeds to box 510. If the answer from decision diamond524 is “yes”, then flow 499 proceeds to box 526 where the test isfinished.

In the foregoing specification, the invention has been described withreference to specific embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the present invention as set forthin the claims below. For example, the embodiments described above havebeen described in the context of memories. However, alternateembodiments may use the method and apparatus described herein in anydesired context. Memories are just one possible context. Accordingly,the specification and figures are to be regarded in an illustrativerather than a restrictive sense, and all such modifications are intendedto be included within the scope of present invention. Note that the term“couple” has been used to denote that one or more addition conductiveelements may be interposed between two elements that are coupled.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the terms“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus.

1. A method comprising: providing a first coarse voltage level;providing a first fine voltage level to a control gate of a memory cell,the first fine voltage level based on the first coarse voltage level;reading the memory cell to determine conductivity of the memory cellwith the first fine voltage level provided to the control gate;providing a second fine voltage level to the control gate of the memorycell, the second fine voltage level based on the first coarse voltagelevel; reading the memory cell to determine conductivity of the memorycell with the second fine voltage level provided to the control gate;providing a second coarse voltage level; providing a third fine voltagelevel to the control gate of the memory cell, the third fine voltagelevel based on the second coarse voltage level; reading the memory cellto determine conductivity of the memory cell with the third fine voltagelevel provided to the control gate; providing a fourth fine voltagelevel to the control gate of the memory cell, the fourth fine voltagelevel based on the second coarse voltage level; reading the memory cellto determine conductivity of the memory cell with the fourth finevoltage level provided to the control gate.
 2. The method of claim 1further comprising: providing a third coarse voltage level; providing afifth fine voltage level to the control gate of the memory cell, thefifth fine voltage level based on the third coarse voltage level;reading the memory cell to determine conductivity of the memory cellwith the fifth fine voltage level provided to the control gate;providing a sixth fine voltage level to the control gate of the memorycell, the sixth fine voltage level based on the third coarse voltagelevel; reading the memory cell to determine conductivity of the memorycell with the sixth fine voltage level provided to the control gate. 3.The method of claim 1 further comprising: providing a fifth fine voltagelevel to the control gate of the memory cell, the fifth fine voltagelevel based on the first coarse voltage level; reading the memory cellto determine conductivity of the memory cell with the fifth fine voltagelevel provided to the control gate; providing a sixth fine voltage levelto the control gate of the memory cell, the sixth fine voltage levelbased on the second coarse voltage level; reading the memory cell todetermine conductivity of the memory cell with the sixth fine voltagelevel provided to the control gate.
 4. The method of claim 1 furthercomprising: programming the memory cell prior to the reading the memorycell to determine conductivity of the memory cell with the first finevoltage level provided to the control gate, the reading the memory cellto determine conductivity of the memory cell with the second finevoltage level provided to the control gate, the reading the memory cellto determine conductivity of the memory cell with the third fine voltagelevel provided to the control gate, and the reading the memory cell todetermine conductivity of the memory cell with the fourth fine voltagelevel provided to the control gate.
 5. The method of claim 1 wherein:the providing the first fine voltage level to the control gate of thememory cell includes providing the first fine voltage level to controlgates of a plurality of memory cells of an array; the reading the memorycell to determine conductivity of the memory cell with the first finevoltage level provided to the control gate includes reading theplurality of memory cells to determine conductivity of the plurality ofmemory cells with the first fine voltage level provided to the controlgates of the plurality of memory cells; the providing the second finevoltage level to the control gate of the memory cell includes providingthe second fine voltage level to control gates of a plurality of memorycells of the array; the reading the memory cell to determineconductivity of the memory cell with the second fine voltage levelprovided to the control gate includes reading the plurality of memorycells to determine conductivity of the plurality of memory cells withthe second fine voltage level provided to the control gates of theplurality of memory cells; the providing the third fine voltage level tothe control gate of the memory cell includes providing the third finevoltage level to control gates of the plurality of memory cells of thearray; the reading the memory cell to determine conductivity of thememory cell with the third fine voltage level provided to the controlgate includes reading the plurality of memory cells to determineconductivity of the plurality of memory cells with the third finevoltage level provided to the control gates of the plurality of memorycells; the providing the fourth fine voltage level to the control gateof the memory cell includes providing the fourth fine voltage level tocontrol gates of a plurality of memory cells of the array; the readingthe memory cell to determine conductivity of the memory cell with thefourth fine voltage level provided to the control gate includes readingthe plurality of memory cells to determine conductivity of the pluralityof memory cells with the fourth fine voltage level provided to thecontrol gates of the plurality of memory cells.
 6. A method of claim 1wherein: the providing a first fine voltage level to the control gate ofthe memory cell includes coupling a first node of a resistor ladder tothe control gate while the first coarse voltage level is utilized to seta voltage of a second node of the resistor ladder; the providing thesecond fine voltage level to the control gate of the memory cellincludes coupling a third node of the resistor ladder to the controlgate while the first coarse voltage level is utilized to set the voltageof the second node of the resistor ladder.
 7. A method of claim 6wherein: the providing a third fine voltage level to the control gate ofthe memory cell includes coupling the first node of the resistor ladderto the control gate while the second coarse voltage is utilized to setthe voltage of the second node of the resistor ladder; the providing thefourth fine voltage level to the control gate of a memory cell includescoupling the third node of the resistor ladder to the control gate whilethe second coarse voltage is utilized to set the voltage of a secondnode of the resistor ladder.
 8. The method of claim 1 wherein: the firstfine voltage level is within approximately 100 millivolts of the secondfine voltage level; the first coarse voltage level is approximately onevolt or greater from an adjacent coarse voltage level.
 9. The method ofclaim 1 wherein a maximum fine voltage level is fixed during theproviding the first fine voltage level, the providing the second finevoltage level, the providing the third fine voltage level, and theproviding the fourth fine voltage level.
 10. A memory comprising: anarray, the array including a plurality of memory cells, each memory cellof plurality of memory cells including a control gate; decode circuitryincluding a plurality of outputs coupled to control gates of the memorycells of the plurality of memory cells, an adjustable voltage supplyincluding an output whose voltage is adjustable, the output of theadjustable supply voltage is coupled to the decode circuitry, whereinthe decode circuitry is operable to couple the output of the adjustablevoltage supply to control gates of the plurality of memory cells,wherein the adjustable voltage supply includes: a resistor ladder havinga plurality of nodes located along the resistor ladder; a multiplexerhaving a plurality of inputs and an output, each input of the pluralityof inputs is coupled to a node of the plurality of nodes of the resistorladder, the output of the multiplexer is coupled to the output of theadjustable voltage supply; a control input, wherein a voltage of eachnode of the plurality of nodes is based upon a voltage received at thecontrol input, wherein the voltage received at the control input isadjustable.
 11. The memory of claim 10 wherein the adjustable voltagesupply circuit includes: a second resistor ladder including a secondplurality of nodes; a second multiplexer including a second plurality ofinputs, each input of the second plurality of inputs is coupled to anode of the second plurality of nodes, the output of the secondmultiplexer is coupled to the control input.
 12. The memory of claim 11wherein: each node of the first plurality of nodes of the first resistorladder is spaced apart from an adjacent node of the first plurality ofnodes of the first resistor ladder by a resistive circuit located inbetween; each node of second plurality of nodes of the second resistorladder is spaced apart from an adjacent node of the second plurality ofnodes of the second resistor ladder by a resistive circuit located inbetween; the resistor circuits between the nodes of the first pluralityof nodes have a smaller resistance value than the resistor circuitsbetween the nodes of the second plurality nodes.
 13. The memory of claim11 wherein: an end node of the resistor ladder is connected to an endnode of the second resistor ladder.
 14. The memory of claim 10 whereinthe output of the adjustable voltage supply is coupled to the decodecircuitry via a block switch circuit.
 15. The memory of claim 10 whereinthe output of the adjustable voltage supply is coupled to a well biasingcircuit, the well biasing circuit controlling the well bias of theplurality of memory cells.
 16. The memory of claim 10 furthercomprising: controller including a first set of control outputs forcontrolling which input of the multiplexer is connected to themultiplexer output, the controller including a second set of outputs forcontrolling the decode circuitry; the controller is configured during avoltage threshold test to provide control signals to the decodecircuitry to couple the control gates of the plurality of memory cellsto the output of the adjustable voltage circuit and to provide controlsignals to the multiplexer to couple, one at a time, nodes of theplurality of nodes of the resistor ladder during the voltage thresholdtest to apply different voltage levels to the control gates of theplurality of memory cells.
 17. The memory of claim 10 wherein thevoltage adjusting circuit includes: a voltage control circuit coupled toa first node of the plurality of nodes to control the voltage of a firstnode of the plurality of nodes, wherein the voltage of other nodes ofthe plurality of nodes of the resistor ladder is based upon the voltageof the first node, the voltage control circuit having an input coupledto the control input.
 18. The memory of claim 10 wherein each memorycell of the plurality of memory cells is characterized as a flash memorycell.
 19. A circuit comprising: a resistor ladder including a pluralityof nodes located along the resistor ladder; wherein each node of theplurality of nodes of the resistor ladder is spaced apart from anadjacent node of the plurality of nodes of the resistor ladder by aresistive circuit located in between; a multiplexer having a pluralityof inputs, each input of the plurality of inputs is coupled to a node ofthe plurality of nodes of the resistor ladder; a voltage control circuitcoupled to a second node of the plurality of nodes to control a voltageof a second node, wherein the voltage of other nodes of the plurality ofnodes of the resistor ladder is based upon the voltage of the secondnode, the voltage control circuit having an input, the voltage of thesecond node is based upon a voltage received at the input; a secondresistor ladder including a second plurality of nodes, wherein an endnode of the resistor ladder is connected to an end node of the secondresistor ladder; a second multiplexer including a second plurality ofinputs, each input of the second plurality of inputs is coupled to anode of the second plurality of nodes, the output of the secondmultiplexer is coupled to the input of the voltage control circuit. 20.The circuit of claim 19 wherein: wherein each node of the secondplurality of nodes of the second resistor ladder is spaced apart from anadjacent node of the second plurality of nodes of the second resistorladder by a resistive circuit located in between, wherein the resistorcircuits between the nodes of the first plurality of nodes have asmaller resistance value than the resistor circuits between the nodes ofthe second plurality nodes.
 21. The circuit of claim 19 wherein thefirst plurality of inputs is of a greater number than the secondplurality of inputs.
 22. The circuit of claim 19 wherein the end node ofthe resistor ladder and the end node of the second resistor ladder arecoupled to an external voltage pin via a switch.